The Hardware That Makes Virtual Machines Possible
Running a guest operating system that believes it owns the machine used to require interpreting or rewriting its privileged instructions. Hardware virtualization support added a mode below the kernel's, so a guest can run its own privileged code at native speed while the hypervisor stays in control — and a second layer of address translation so guest memory works without the hypervisor intervening on every access.
Software view, hardware view
The gap between what you wrote and what the machine does is where this whole domain lives.
The problem hardware support solved
A guest kernel expects to execute privileged instructions — installing page tables, masking interrupts, changing privilege level. Left alone on real hardware it would either fail or, worse, actually succeed and take over the machine. Early virtualization solved this in software: trap-and-emulate where the architecture cooperated, and binary translation rewriting instruction streams where it did not. Both worked and both were slow, particularly for kernel-heavy workloads.
Hardware virtualization support restructured the problem by adding a mode *beneath* the kernel's existing privilege levels (Why Kernel Mode Is Actually Privileged). The guest kernel runs at what it believes is full privilege, but inside a container whose escape hatches the hypervisor configures. Sensitive operations cause a transition to the hypervisor — conventionally called a VM exit — which handles them and resumes the guest. Everything else runs natively at full speed.
The performance model follows directly from that design: guest code that does not exit is native speed; the cost is the exits. This is why a compute-bound loop in a VM performs essentially like bare metal, while an I/O-heavy or interrupt-heavy workload can show noticeable overhead. Reducing exit frequency has been the central optimisation target of virtualization for two decades, which is why paravirtualized drivers and device passthrough exist.
| Approach | How privileged instructions are handled | Speed of ordinary guest code | Main cost |
|---|---|---|---|
| Full emulation | Interpreted by the emulator | Far slower than native | Every instruction is interpreted |
| Binary translation | Rewritten ahead of execution | Close to native for user code | Translation complexity; kernel paths still slow |
| Paravirtualization | Guest is modified to call the hypervisor deliberately | Near native | Requires a modified guest kernel |
| Hardware-assisted | Executed directly; sensitive ones trap to the hypervisor | Native between exits | The exits themselves, and their frequency |
Two layers of address translation
The second half of the problem is memory. The guest kernel builds page tables mapping guest-virtual to what it believes is physical memory. But guest-physical is itself a fiction the hypervisor maintains, so a second mapping is needed from guest-physical to host-physical. Doing that in software meant the hypervisor maintaining shadow page tables and intercepting every guest page-table update — correct, and very expensive.
Second-level address translation puts that mapping in hardware. The MMU walks the guest's tables to get a guest-physical address, then walks the hypervisor's tables to get a host-physical one, without the hypervisor being involved (The MMU: Translation and Protection in One Check, The Page-Table Walk: Dependent Loads All the Way Down). Guest page-table updates become ordinary memory writes rather than trapped operations, which removed a large source of exits.
The cost is that a TLB miss is now more expensive, because a full walk traverses two levels of tables rather than one — a nested walk touching substantially more memory than a native one (When Translation Itself Is the Bottleneck). This is the concrete reason TLB pressure matters more inside a VM than outside, and why huge pages often show a larger benefit in virtualised environments (Huge Pages: More Coverage per Entry, and What It Costs).
What this does and does not isolate
Hardware virtualization gives a strong architectural boundary: the guest cannot read host memory or another guest's memory, cannot escape its privilege container without a hypervisor defect, and sees a consistent machine abstraction. That is a genuinely robust isolation primitive and is why VMs remain the boundary of choice for mutually distrusting tenants.
What it does not virtualize is the *microarchitecture*. Guests on the same physical core share caches, predictors, translation buffers, memory bandwidth and the interconnect. Those are not partitioned by the virtualization extensions, so a noisy neighbour affects your performance and, as Side Channels: When Performance Optimisations Leak and Spectre and Meltdown: When Speculation Crossed a Boundary showed, may in some circumstances observe something about your execution.
This is the sharp distinction from containers, which do not use these mechanisms at all: containers are OS-level isolation — separate namespaces and resource limits over a *shared kernel* — so their boundary is the kernel's system-call surface rather than a hardware-enforced one. Neither is universally better; the cloud domain treats the comparison, its performance implications and when to choose which in Containers vs Virtual Machines, and this domain's contribution is only the hardware mechanism underneath the VM side.
- Architecturally strong — memory and privilege isolation are enforced by hardware, not convention.
- Microarchitecturally shared — caches, predictors and bandwidth are not virtualized, which is where noisy neighbours live.
- Exits are the cost — guest code runs natively between them, so exit frequency determines overhead.
- Nested walks are more expensive — two levels of page tables make TLB misses cost more inside a VM.
- Containers are a different mechanism entirely — shared kernel, namespace isolation, no hardware virtualization involved.
Key points
- Hardware support added a mode beneath the kernel's, so a guest runs privileged code directly and traps only for operations that must be mediated.
- Performance follows from exit frequency: code that does not exit runs at native speed.
- Second-level address translation maps guest-physical to host-physical in hardware, removing the shadow-page-table cost.
- The price is a nested page walk, so TLB misses are more expensive inside a VM than outside it.
- The boundary is architecturally strong but microarchitecturally shared, which is where noisy neighbours and side channels live.
Follow the mechanism
The path through the machine, hop by hop — and the conclusions it invites that are wrong.
- 1Guest instruction → CPU: ordinary instructions execute directly on the physical core with no hypervisor involvement.
- 2Sensitive operation → VM exit: an operation the hypervisor must mediate causes a transition out of guest mode.
- 3Hypervisor → emulate and resume: the operation is handled, state is updated, and the guest resumes where it left off.
- 4Guest virtual address → nested walk: the MMU walks guest tables to a guest-physical address, then hypervisor tables to a host-physical one (The Page-Table Walk: Dependent Loads All the Way Down).
- 5Translation → TLB: the completed translation is cached, so subsequent accesses skip both walks entirely (The TLB: A Cache for Addresses, Not Data).
- • "A VM emulates the CPU, so it must be much slower" — guest code executes natively; only mediated operations cost extra.
- • "Virtualization overhead is a fixed percentage" — it depends entirely on how often the workload triggers exits.
- • "The hypervisor isolates everything" — it isolates architectural state; caches, predictors and bandwidth remain shared.
- • "Containers are lightweight VMs" — they are a different mechanism with a different boundary, not a faster implementation of the same one.
Consequences, controls and cost
- • Compute-bound workloads run in a VM at close to bare-metal speed, while exit-heavy workloads show clear overhead.
- • TLB pressure has a larger effect inside a VM because each miss costs a nested walk.
- • Huge pages often deliver a bigger improvement in virtualised environments than on bare metal.
- • Device passthrough and paravirtualized drivers exist specifically to cut exit frequency for I/O.
- • Choose instance types and drivers that minimise exits for your workload — paravirtualized or passthrough devices for I/O-heavy work.
- • Consider huge pages, which reduce nested-walk cost more inside a VM than on bare metal.
- • Use dedicated hosts or instances when microarchitectural sharing is a performance or security concern.
- • Benchmark inside the target environment rather than on bare metal, since the overhead is workload-shaped and hard to predict.
- • Match the isolation mechanism to the threat model: hardware virtualization for mutually distrusting tenants, containers where a shared kernel is acceptable.
- • Compare the same workload inside and outside a VM to size the overhead for your specific code rather than assuming a figure.
- • Watch TLB miss counters inside the guest, since nested walks make each miss more costly.
- • Look at exit-related metrics where the hypervisor exposes them; exit rate predicts overhead better than CPU utilisation does.
- • Test with and without huge pages in the guest, as the benefit is often larger than on bare metal.
- • Strong isolation costs exits, memory overhead per guest and a nested-walk penalty that bare metal does not pay.
- • Device passthrough reduces overhead but sacrifices live migration and some operational flexibility.
- • Dedicated hardware removes noisy-neighbour and co-tenancy exposure at significantly higher cost.
- • Huge pages reduce translation cost but bring fragmentation and allocation complexity.
Scope
§224 — what these claims are specific to.
- PLATFORM-SPECIFICVendors implement and name these extensions differently, and exit conditions, nested-walk costs and available optimisations differ between x86-64 and AArch64 and between generations of each.
- SIMPLIFIEDThe two-level translation diagram omits caching of intermediate walk results and other optimisations that reduce nested-walk cost substantially on modern hardware.
- GENERALThe structural conclusion — architectural isolation is enforced, microarchitectural resources are shared — holds across hardware-assisted virtualization implementations.